Vias are routinely used in forming ICs. Vias may be formed that extend vertically from the bottom side of an IC die to one of the metal interconnect layers on the active top side of the IC die. Such structures are often referred to as “through-silicon vias”, and are referred to more generally herein as through-substrate vias (TSVs).
TSVs are generally framed by a dielectric liner and filled with copper or another electrically conductive TSV filler material to provide the desired low resistance vertical electrical connection. A diffusion barrier metal formed on the dielectric liner frames the TSV and protects against escape of the TSV filler material into the substrate in the case of highly mobile metal TSV filler materials that are known to significantly reduce minority carrier lifetimes, such as copper in silicon, that cause problems such as significantly increased junction leakage or a shift in transistor threshold voltage.
Copper, as well as some other TSV filler materials, have a significantly higher coefficient of thermal expansion (CTE) as compared to conventional IC substrates, such as silicon. For example, copper has a CTE of approximately 17 ppm/° C., whereas silicon has a CTE of approximately 2 to 3 ppm/° C. This CTE mismatch (ΔCTE) can result in significant thermally induced stress in the silicon including the circuitry (e.g. MOS transistors) in the silicon surrounding the TSVs, particularly during certain fab processing subsequent to the fabrication of the TSV (e.g., 360 to 410° C. sinters), during assembly and test/operations as may occur during solder reflow (e.g., up to about 260° C.) or during thermo-compressive bonding (e.g., up to 400° C.), during certain temperature cycle reliability testing (e.g., −55° C. to 125° C.), or even during long-term field operation of the IC.
A number of solutions have been proposed to reduce problems caused by CTE mismatches for ICs having copper TSVs. In some IC designs, to reduce stress, TSVs are positioned in TSV arrays comprising a plurality of TSVs. For example, reducing the TSV diameter and increasing TSV spacing (i.e. pitch) generally reduces stress. Another known option to reduce stress is to use a TSV filler material that provides a lower ΔCTE relative to the substrate, such as tungsten instead of copper.